AI 导读
CS-4 在此取得进展。片外 I/O 从 1.2Tb/s 翻倍至 2.4Tb/s，因为晶圆的并行 I/O 随 2 倍时钟提升而扩展。在此之上还有一个新的 Wafer I/O 模块：一块可现场升级的 FPGA NIC，将 Cerebras 的专有 I/O 转换为标准以太网。这听起来微不足道，但这意味着网络无需重新设计机箱即可演进，也让晶圆能说客户网络架构所说的任何协议。(2/3)
正文
CS-4 makes progress here. Off-wafer I/O doubles from 1.2Tb/s to 2.4Tb/s, since the wafer's parallel I/O scales with the 2x clock bump. On top of that sits a new Wafer I/O module: a field-upgradeable FPGA NIC that converts Cerebras's proprietary I/O to standard ethernet. That sounds minor, but it means networking can evolve without a chassis redesign, and it lets the wafer speak whatever the customer's fabric speaks. (2/3)
来源：@SemiAnalysis_ · x.com