HiCache sits between HBM and the external DRAM KV store as a per-rank host-side L2 buffer, so every load and offload takes an extra copy, the L3-to-L2 fetch is not pipelined with compute, and under MLA with TP each rank replicates the same KV across PCIe and host memory while making eviction decisions on local information only.

UMBP through the SGLang KVCache Store Linker replaces that with a direct, layer-wise pipelined HBM-to-DRAM path into a single shared per-node pool, which removes the intermediate copy and stall, deduplicates the replicated KV, and lets placement and eviction be decided globally across DP ranks and instances. (3/3)