AI 导读
片外带宽一直是晶圆级芯片的弱点。WSE-3 拥有惊人的晶圆上 SRAM 带宽，但数据一旦需要离开晶圆，一切都会变慢。这很重要，因为晶圆只能容纳 44GB 的 SRAM，所以大模型会被分散到多块晶圆上，每多一块晶圆就意味着更多流量要穿过那条匮乏的 I/O 路径。长上下文会让情况更糟，因为 KV cache 会进一步推高晶圆数量。(1/3)🧵 图片来源：Cerebras
正文
Off-chip bandwidth has always been the weak point of wafer-scale. The WSE-3 has staggering on-wafer SRAM bandwidth, but everything slows down the moment data has to leave the wafer. That mattered because the wafer only holds 44GB of SRAM, so big models get spread across many wafers, and every extra wafer means more traffic crossing that starved I/O path. Long context makes it worse, since KV cache balloons the wafer count further. (1/3)🧵
Image Source: Cerebras
来源：@SemiAnalysis_ · x.com