Huawei's answer to the per-chip gap is a 3D-stacking technique it calls LogicFolding. Instead of printing denser transistors, LogicFolding stacks logic dies on top of each other, aiming for the transistor density of a 1.4 nm process by 2031 using 5 nm-class dies. But LogicFolding isn’t set to appear in an Ascend chip before 2030.